1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the semiconductor device, and is applied, for example, to a high-breakdown-voltage transistor.
2. Description of the Related Art
In recent years, in order to realize high integration density and low cost, semiconductor devices, such as NAND flash memories, are configured such that a contact cell is not provided for each bit. Owing to this configuration, a memory cell region is excessively small. The density of the memory cell region has been increasing, as the generation of processing technology progresses.
On the other hand, in fact, the operation voltages of the NAND flash memory, such as write, erase and read voltages, have not been decreasing with the progress of the generation progresses. The reason is as follows. In a write operation of the NAND flash memory, a high voltage of, e.g. about 15 V to 30 V, is applied to the word line (gate) and the bit line (drain). Electrons, which occur near the drain, become able to tunnel a potential barrier, and electrons flow into the floating gate. Thus, the threshold voltage for the electric current needs to be increased.
The write/erase/read voltages are transferred from high-breakdown-voltage transistors in peripheral circuits (circuits for amplification/boost) which are provided in the vicinity of the memory cell array and control high voltages. Since high voltages due to such operation voltages are applied to the high-breakdown-voltage transistors, it is necessary to secure such an occupation area as to maintain a surface breakdown voltage and a junction breakdown voltage.
Thus, if the surface breakdown voltage and junction breakdown voltage are to be improved, there is a tendency that the occupation area increases, and this is disadvantageous for microfabrication.
As described above, in the conventional semiconductor device and the fabrication method thereof, if the surface breakdown voltage and junction breakdown voltage are to be maintained, there is a tendency that the occupation area increases, and this is disadvantageous for microfabrication.
Jpn. Pat. Appln. KOKAI Publication No. H02-67765, for instance, discloses a semiconductor device including a high-breakdown-voltage MOS transistor.